;/**
; * @file		_chiptop.inc 
; * @brief		Definition Chip-Top I/O register
; * @note		None
; * @attention	None
; * 
; * <B><I>Copyright 2016 Socionext Inc.</I></B>
; */

CHIPTOPBase		EQU	0x4D020000

;; **** Clock Area (0x4D02_1000) ****
CLKSEL1			EQU	(CHIPTOPBase + 0x1000)
CLKSEL2			EQU	(CHIPTOPBase + 0x1004)
CLKSEL3			EQU	(CHIPTOPBase + 0x1008)
CLKSEL4			EQU	(CHIPTOPBase + 0x100C)
CLKSEL5			EQU	(CHIPTOPBase + 0x1010)
CLKSEL6			EQU	(CHIPTOPBase + 0x1014)
CLKSEL7			EQU	(CHIPTOPBase + 0x1018)
CLKSEL8			EQU	(CHIPTOPBase + 0x101C)
CLKSEL9			EQU	(CHIPTOPBase + 0x1020)
CLKSEL10		EQU	(CHIPTOPBase + 0x1024)
CLKSEL11		EQU	(CHIPTOPBase + 0x1028)
CLKSEL12		EQU	(CHIPTOPBase + 0x102C)
PLLCNT1			EQU	(CHIPTOPBase + 0x1030)
PLLCNT2			EQU	(CHIPTOPBase + 0x1034)
PLLCNT3			EQU	(CHIPTOPBase + 0x1038)
PLLCNT4			EQU	(CHIPTOPBase + 0x103C)
PLLCNT5			EQU	(CHIPTOPBase + 0x1040)
;PLLCNT6		EQU	(CHIPTOPBase + 0x1044)
PLLCNT7			EQU	(CHIPTOPBase + 0x1048)
PLLCNT8			EQU	(CHIPTOPBase + 0x104C)
PLLCNT9			EQU	(CHIPTOPBase + 0x1050)
CLKSTOP1		EQU	(CHIPTOPBase + 0x1054)
CLKSTOP2		EQU	(CHIPTOPBase + 0x1058)
CLKSTOP3		EQU	(CHIPTOPBase + 0x105C)
CLKSTOP4		EQU	(CHIPTOPBase + 0x1060)
CLKSTOP5		EQU	(CHIPTOPBase + 0x1064)
CLKSTOP6		EQU	(CHIPTOPBase + 0x1068)
CLKSTOP7		EQU	(CHIPTOPBase + 0x106C)
CLKSTOP8		EQU	(CHIPTOPBase + 0x1070)
CLKSTOP9		EQU	(CHIPTOPBase + 0x1074)
CLKSTOP10		EQU	(CHIPTOPBase + 0x1078)
CLKSTOP11		EQU	(CHIPTOPBase + 0x107C)
CLKSTOP12		EQU	(CHIPTOPBase + 0x1080)
CLKSTOP13		EQU	(CHIPTOPBase + 0x1084)
CLKSTOP14		EQU	(CHIPTOPBase + 0x1088)
CRSWR			EQU	(CHIPTOPBase + 0x108C)
CRRRS			EQU	(CHIPTOPBase + 0x1090)
CRRSM			EQU	(CHIPTOPBase + 0x1094)

;; **** PORT Area (0x4D02_2000) ****
PDR76			EQU	(CHIPTOPBase + 0x200C)
PDR98			EQU	(CHIPTOPBase + 0x2010)
PDRBA			EQU	(CHIPTOPBase + 0x2014)
PDRDC			EQU	(CHIPTOPBase + 0x2018)
PDRFE			EQU	(CHIPTOPBase + 0x201C)
PDRHG			EQU	(CHIPTOPBase + 0x2020)
PDRJW			EQU	(CHIPTOPBase + 0x2024)
PDRLK			EQU	(CHIPTOPBase + 0x2028)
PDRNM			EQU	(CHIPTOPBase + 0x202C)
PDRPY			EQU	(CHIPTOPBase + 0x2030)
DDR76			EQU	(CHIPTOPBase + 0x210C)
DDR98			EQU	(CHIPTOPBase + 0x2110)
DDRBA			EQU	(CHIPTOPBase + 0x2114)
DDRDC			EQU	(CHIPTOPBase + 0x2118)
DDRFE			EQU	(CHIPTOPBase + 0x211C)
DDRHG			EQU	(CHIPTOPBase + 0x2120)
DDRJW			EQU	(CHIPTOPBase + 0x2124)
DDRLK			EQU	(CHIPTOPBase + 0x2128)
DDRNM			EQU	(CHIPTOPBase + 0x212C)
DDRPY			EQU	(CHIPTOPBase + 0x2130)
EPCR76			EQU	(CHIPTOPBase + 0x220C)
EPCR98			EQU	(CHIPTOPBase + 0x2210)
EPCRBA			EQU	(CHIPTOPBase + 0x2214)
EPCRDC			EQU	(CHIPTOPBase + 0x2218)
EPCRFE			EQU	(CHIPTOPBase + 0x221C)
EPCRHG			EQU	(CHIPTOPBase + 0x2220)
EPCRJW			EQU	(CHIPTOPBase + 0x2224)
EPCRLK			EQU	(CHIPTOPBase + 0x2228)
EPCRNM			EQU	(CHIPTOPBase + 0x222C)
EPCRPY			EQU	(CHIPTOPBase + 0x2230)
PUDER76			EQU	(CHIPTOPBase + 0x230C)
PUDER98			EQU	(CHIPTOPBase + 0x2310)
PUDERBA			EQU	(CHIPTOPBase + 0x2314)
PUDERDC			EQU	(CHIPTOPBase + 0x2318)
PUDERFE			EQU	(CHIPTOPBase + 0x231C)
PUDERHG			EQU	(CHIPTOPBase + 0x2320)
PUDERJW			EQU	(CHIPTOPBase + 0x2324)
PUDERLK			EQU	(CHIPTOPBase + 0x2328)
PUDERNM			EQU	(CHIPTOPBase + 0x232C)
PUDERPY			EQU	(CHIPTOPBase + 0x2330)
PUDCR76			EQU	(CHIPTOPBase + 0x240C)
PUDCR98			EQU	(CHIPTOPBase + 0x2410)
PUDCRBA			EQU	(CHIPTOPBase + 0x2414)
PUDCRDC			EQU	(CHIPTOPBase + 0x2418)
PUDCRFE			EQU	(CHIPTOPBase + 0x241C)
PUDCRHG			EQU	(CHIPTOPBase + 0x2420)
PUDCRJW			EQU	(CHIPTOPBase + 0x2424)
PUDCRLK			EQU	(CHIPTOPBase + 0x2428)
PUDCRNM			EQU	(CHIPTOPBase + 0x242C)
PUDCRPY			EQU	(CHIPTOPBase + 0x2430)

;; **** JTSCR Area (0x4D02_0000) ****
PERSEL1			EQU	(CHIPTOPBase + 0x0000)
PERSEL2			EQU	(CHIPTOPBase + 0x0004)
PERSEL3			EQU	(CHIPTOPBase + 0x0008)
PERSEL4			EQU	(CHIPTOPBase + 0x000C)
MSELC			EQU	(CHIPTOPBase + 0x0010)
DBCNT1			EQU	(CHIPTOPBase + 0x0014)
DBCNT2			EQU	(CHIPTOPBase + 0x0018)
DBCNT3			EQU	(CHIPTOPBase + 0x001C)
DBCNT4			EQU	(CHIPTOPBase + 0x0020)
DBCNT5			EQU	(CHIPTOPBase + 0x0024)
PUDCNT			EQU	(CHIPTOPBase + 0x0028)

	END
